Intel® MAX® 10 FPGA – AN 488: Stepper Motor Controller Design Example: Intel MAX 10 FPGA Development Kit

Intel® MAX® 10 FPGA – AN 488: Stepper Motor Controller Design Example: Intel MAX 10 FPGA Development Kit

715050
5/26/2016

Introduction

The advantage of precision control, open-loop control of the motor, self-contained braking, and the absence of brushes makes the stepper motor a convenient choice for a variety of specialized applications.

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0

IP Cores (1)
IP Core IP Core Category
Internal Oscillator ClocksPLLsResets

Detailed Description

Printers and plotters, disk drives, robots, CNC machines, and other precision machines are common examples where the stepper motor is used extensively

A stepper motor's operation can be explained by considering a series of electromagnets arranged in a circle to encapsulate a rotor made up of a magnetic material. When these solenoids, or electromagnets, are energized in sequence, the magneto motive force (MMF) developed in them interacts with the rotor and causes it to re-align to the magnetic field, thereby causing it to rotate in a clockwise or counterclockwise direction. The motor's angular displacement can be controlled by simply switching these electromagnets on or off in a fixed pattern for the desired motion of the motor.

The motor controller implemented in this design uses a MAX 10 device to govern (as you have predetermined) the performance and operation of a unipolar permanent magnet stepper motor. The design uses a few switches and buttons on the demo board to serve as the user interface. This motor controller design offers the following advantages: - Two types of control for starting and stopping the motor and selecting forward or reverse rotation: manual control (through the user interface) or automatic control (through a microcontroller). - Two modes of operation: continuous mode and step mode. - Eliminates the need for an external clock signal as all MAX 10 devices have a unique internal oscillator which is incorporated in this design.



Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.0.0 Standard


Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0