Design Store


Remote System Upgrade over UART based on Nios II Processor with EPCQ  


CategoryDesign Example
NameRemote System Upgrade over UART based on Nios II Processor with EPCQ
DescriptionThe design example implements basic remote configuration features in Nios II-based systems with EPCQ for Cyclone V E FPGA device. The UART interface is used to provide the remote configuration functionality. The UART terminal allows you to upload new FGPA designs for both user hardware and user software, at the same time you can also trigger reconfiguration from factory image to user image through the UART terminal.
Operating SystemNone
IP Core
IP CoreHeading
Altera Serial Flash ControllerFlash
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
PIO (Parallel I/O)Other
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Altera PLLClocksPLLsResets
Altera Remote UpdateConfigurationProgramming
Altera Remote Update CoreConfigurationProgramming
Reset ControllerQsysInterconnect
System ID PeripheralOther
UART (RS-232 Serial Port)Other
Version1.0
FamilyCyclone V
Device5CEFA7
Documentation
DocumentDescription
Remote System Upgrade over UART based on Nios II Processor with EPCQThis is Reference Guide for the design example.
Development KitCyclone V E FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/cv_e_rsu_uart.par

Once the process completes, then type:

quartus_sh --platform –name cv_e_rsu_uart

Download   (The download link will expire on April 17, 2021, 7:27 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Dec. 22, 2016, 9:51 a.m.