Design Store


Nios II Simple Socket Server Ethernet Example for CVGT  


CategoryDesign Example
NameNios II Simple Socket Server Ethernet Example for CVGT
DescriptionThis design example shows a socket server using the NicheStack TCP/IP stack-Nios® II Edition on MicroC/OS-II on a Cyclone V GT development board. The server implements simple commands to control board LEDs through a separate MicroC/OS-II task.
Operating SystemNone
IP Core
IP CoreHeading
Nios II Gen2 ProcessorNiosII
Altera PLLClocksPLLsResets
Avalon-ST AdapterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Reset ControllerQsysInterconnect
Scatter-Gather DMA ControllerBridgesAndAdaptors
Triple-Speed EthernetEthernet
Generic Tri-State ControllerOther
Tristate Controller AggregatorQsysInterconnect
Tristate Controller TranslatorQsysInterconnect
IRQ MapperQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
PIO (Parallel I/O)Other
Interval TimerPeripherals
JTAG UARTConfigurationProgramming
Performance Counter UnitArithmetic
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
External Memory DLL blockExternalMemoryInterfaces
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
External Memory OCT blockExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
Abstract DRAM Memory ModelExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
System ID PeripheralOther
Tri-State Conduit BridgeQsysInterconnect
Version1.0
FamilyCyclone V
Device5CGTFD9
Documentation
DocumentDescription
CVGT Nios II Simple Socket Server Quick Reference GuideThis document applies for ACDS 15.1 as well
Using the NicheStack TCP/IP Stack - Nios II Tutorial-
Development KitCyclone V GT FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/cvgt_simple_socket_server.par

Once the process completes, then type:

quartus_sh --platform –name cvgt_simple_socket_server

Download   (The download link will expire on Oct. 21, 2021, 11:48 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Feb. 13, 2017, 1:43 p.m.