Cyclone® V FPGA – Nios® II Processor "Hello World" with LCD Character Display Design Example

Cyclone® V FPGA – Nios® II Processor "Hello World" with LCD Character Display Design Example

714891
6/3/2016

Introduction

This design example uses a Nios® II soft processor to print "Hello World from Nios II!" in the console and display the same on the LCD character display on this kit. It also connects the User Push Buttons to the User LEDs in either hardware or software, which allows the user to turn on or turn off the LEDs. This is a "from the ground up" tutorial. Some of the appendices describe things like schematic capture, using interrupts to detect GPIO changes, and using the bit-banging technique to drive the LCD character display.

Development Kit

Cyclone® V E FPGA Development Kits

Design Details

Device Family

Cyclone® V FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
IP Cores (18)
IP Core IP Core Category
IRQ Mapper QsysInterconnect
PIO (Parallel I/O) Other
MM Interconnect QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Reset Controller QsysInterconnect
JTAG UART ConfigurationProgramming

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.0.0 Standard


Development Kit

Cyclone® V E FPGA Development Kits

Design Details

Device Family

Cyclone® V FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0