Intel® MAX® 10 FPGA – AN 495: IDE/ATA Controller Design Example

Intel® MAX® 10 FPGA – AN 495: IDE/ATA Controller Design Example

714749
5/17/2016

Introduction

Storage devices, such as floppy drives, CD-ROM drives, and hard disk drives, are connected to the computer through the IDE/ATA interface.

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0

IP Cores (0)

Detailed Description

This design example illustrates the implementation of an IDE/ATA controller using an Intel® MAX® 10 FPGA through which a host computer or microprocessor system can connect to a standard Integrated Drive Electronics (IDE) device. When controllers and hard drives had proprietary technologies, a controller from one manufacturer did not work well with a hard drive from another manufacturer. The IDE was created to standardize the use of hard drives in computers. This was based on a concept of combining the controller and the hard drive, thereby reducing interface costs and making firmware implementations easier. The controller residing on a chip provided the means for transferring data to or from the host computer.


This IDE controller, also known as the Advanced Technology Attachment (ATA) controller, is an asynchronous parallel interface between a host microprocessor system and a standard IDE device. Therefore, this can be called a host adapter because it provides a way to connect a complete IDE device to the host.


From the time of its inception, the ATA interface has been upgraded frequently and newer versions have been introduced. This design example implements an IDE controller compatible with the ATA-5 interface. Although the ATA-5 standard supports two modes of operation the PIO mode and the DMA mode this design is restricted to only the PIO mode (mode 0) and with only one device connected to the controller (master).



Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0