Intel® MAX® 10 FPGA – Become an FPGA Designer in 4 Hours Lab

Intel® MAX® 10 FPGA – Become an FPGA Designer in 4 Hours Lab

714498
4/28/2016
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Introduction

This training gives the basic skills to design with Intel® FPGAs. The course uses lectures, demonstrations, and labs that can be completed in 4 hours. You will learn about the architectural features of Intel devices, as well as how the Quartus® II design software works. The 6 labs will train you to: 1) Set up a design project 2) Set assignments and compile a design 3) Perform Timing Analysis 4) Perform Power Analysis 5) Download your design to hardware 6) Debug your design with the Signal Tap II Logic Analyzer The course is most beneficial when using the BeMicro MAX® 10 FPGA Evaluation Kit from our partner Arrow. If you choose not to purchase the kit, you can complete all labs except Download and Debug.

Development Kit

BeMicro* MAX 10 FPGA Evaluation Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
Other Tags

BeMicro* MAX 10 FPGA Evaluation Kit
IP Cores (4)
IP Core IP Core Category
Avalon ALTPLL ClocksPLLsResets
FIFO OnChipMemory
Reset Controller QsysInterconnect
SDRAM Controller ExternalMemoryInterfaces

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.0.0 Standard


Development Kit

BeMicro* MAX 10 FPGA Evaluation Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
Other Tags

BeMicro* MAX 10 FPGA Evaluation Kit