|Name||Arria 10 SOC Scalable Multispeed 10M-10G Ethernet Design|
|Description||This reference design describes a scalable Multispeed 10M-10G Ethernet design that demonstrates Ethernet operations of the Altera® Low Latency Ethernet 10G MAC & Arria 10 1G/10G PHY MegaCore® functions targeted on Altera Arria 10 SOC FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations on the TX and RX datapaths.|
|Development Kit||Arria 10 SoC Development Kit|
Download (The download link will expire on Feb. 22, 2020, 3:46 a.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||137 (From 13 Jun 2016 to 06 Dec 2019)|
|Quartus Prime Version||Download Quartus Prime v16.0|
|Quartus Prime Edition||Standard|
Last updated on Aug. 9, 2016, 11:25 p.m.