Design Store

Arria 10 SOC Scalable Multispeed 10M-10G Ethernet Design  

CategoryDesign Example
NameArria 10 SOC Scalable Multispeed 10M-10G Ethernet Design
DescriptionThis reference design describes a scalable Multispeed 10M-10G Ethernet design that demonstrates Ethernet operations of the Altera® Low Latency Ethernet 10G MAC & Arria 10 1G/10G PHY MegaCore® functions targeted on Altera Arria 10 SOC FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations on the TX and RX datapaths.
Operating SystemNone
IP Core
IP CoreHeading
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
SPI (3 Wire Serial)SPI
Low Latency Ethernet 10G MACEthernet
Arria 10 1G/10GbE and 10GBASE-KR PHYEthernet
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Altera IOPLLClocksPLLsResets
Arria 10 Transceiver ATX PLLTransceiverPLL
Arria 10 FPLLClocksPLLsResets
Altera Arria 10 XCVR Reset SequencerOther
Altera In-System Sources & ProbesSimulationDebugVerification
Version1.0
FamilyArria 10
Device10AS066
Documentation
DocumentDescription
Arria10 SOC Scalable Multispeed 10M-10G Ethernet Design User Guide-
Development KitArria 10 SoC Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/Arria10_Soc_Ethernet_Design.par

Once the process completes, then type:

quartus_sh --platform –name Arria10_Soc_Ethernet_Design

Download
Total Downloads154 (From 13 Jun 2016 to 12 Oct 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 9, 2016, 11:25 p.m.