Design Store

Arria 10 HDMI UHD Video Reference Design  

CategoryDesign Example
NameArria 10 HDMI UHD Video Reference Design
DescriptionThe Arria 10 UHD video reference design demonstrates Altera HDMI 2.0 video connectivity IP with a video processing pipeline based on IP cores from the Altera Video and Image Processing Suite.
Operating SystemBareMetal
IP Core
IP CoreHeading
Altera Arria 10 XCVR Reset SequencerOther
Altera IOPLLClocksPLLsResets
RAM: 1-PORTOnChipMemory
ALTCLKCTRLClocksPLLsResets
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Reset ControllerQsysInterconnect
Altera HDMIAudioVideo
Altera PLL ReconfigClocksPLLsResets
Arria 10 FPLLClocksPLLsResets
Altera GPIOOther
Altera GPIO CoreOther
Avalon-ST AdapterQsysInterconnect
Avalon-ST Data Format AdapterQsysInterconnect
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Arria 10 External Memory InterfacesExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
Arria 10 External Memory Interfaces Debug ComponentExternalMemoryInterfaces
Avalon-MM Pipeline BridgeQsysInterconnect
alt_mem_if JTAG to Avalon Master BridgeBridgesAndAdaptors
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Altera Avalon-MM Efficiency Monitor and Protcol Checker CoreQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Arria 10 External Memory Interfaces IOAUX Master componentExternalMemoryInterfaces
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped RouterQsysInterconnect
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
Avalon-ST Pipeline StageQsysInterconnect
System ID PeripheralOther
Avalon-ST Video stream cleanerQsysInterconnect
Video Input BridgeAudioVideo
Clipper II (4K Ready)AudioVideo
Clocked Video Input II (4K Ready)AudioVideo
Clocked Video Output II (4K Ready)AudioVideo
Mixer II (4K Ready)AudioVideo
Scaler IIAudioVideo
Scaler Algorithmic CoreAudioVideo
Frame Buffer II (4K Ready)AudioVideo
Interval TimerPeripherals
Version1.3
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 UHD Video Reference Design Application NoteThe Arria 10 UHD video reference design demonstrates Altera HDMI 2.0 video connectivity IP with a video processing pipeline based on IP cores from the Altera Video and Image Processing Suite.
Arria 10 UHD Video Reference Design Release NotesThe release notes to accompany this release of the Arria 10 UHD Video Reference Design
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/udx10.par

Once the process completes, then type:

quartus_sh --platform –name udx10

Download
Total Downloads230 (From 10 Aug 2016 to 18 Aug 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Dec. 13, 2017, 10:54 a.m.