Design Store

Arria 10 DisplayPort 4KP60 with Video and Image Processing Pipeline Re-Transmit Reference Design  

CategoryDesign Example
NameArria 10 DisplayPort 4KP60 with Video and Image Processing Pipeline Re-Transmit Reference Design
DescriptionThis reference design demonstrates the Altera video connectivity IP, the DisplayPort Sink (RX) and Source (TX) functions by video data loop-through the Video and Image Processing IP pipeline.
Operating SystemNone
IP Core
IP CoreHeading
Altera Arria 10 XCVR Reset SequencerOther
Avalon FIFO MemoryOnChipMemory
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
DisplayPortAudioVideo
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
PIO (Parallel I/O)Other
On-Chip Memory (RAM or ROM)OnChipMemory
Interval TimerPeripherals
System ID PeripheralOther
Clocked Video Input II (4K Ready)AudioVideo
Clocked Video Output II (4K Ready)AudioVideo
Video Input BridgeAudioVideo
Arria 10 External Memory InterfacesExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
Arria 10 External Memory Interfaces IOAUX Master componentExternalMemoryInterfaces
Avalon-MM Pipeline BridgeQsysInterconnect
Mixer II (4K Ready)AudioVideo
Frame Buffer II (4K Ready)AudioVideo
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Arria 10 FPLLClocksPLLsResets
Altera GPIOOther
Altera GPIO CoreOther
Altera IOPLLClocksPLLsResets
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Re-transmit Reference Design User GuideArria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Re-transmit Reference Design User Guide
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/a10_es3_dp_vip.par

Once the process completes, then type:

quartus_sh --platform –name a10_es3_dp_vip

Download
Total Downloads115 (From 14 Jun 2016 to 13 Jun 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


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Last updated on June 25, 2018, 11:40 p.m.