Design Store

Altera PHYLite with Dynamic Reconfiguration Loopback Reference Design  

CategoryDesign Example
NameAltera PHYLite with Dynamic Reconfiguration Loopback Reference Design
DescriptionThis is PHYLite hardware reference design that is targeting Arria 10 FPGA Development kit. The reference design provides the ability to perform dynamic reconfiguration to the PHYLite IP cores using Nios II soft
processor in a loopback system.
Operating SystemOther
IP Core
IP CoreHeading
Altera PHYLite for memoryTransceiverPHY
PHYLite Core Component for 20nm FamiliesSerialLite
Altera IOPLLClocksPLLsResets
PIO (Parallel I/O)Other
Avalon-MM Pipeline BridgeQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
Reset ControllerQsysInterconnect
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note This application note showcases loopback reference designs using the Altera PHYLite IP core.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/phylite_top_1DQS_2DQ_800MHZ.par

Once the process completes, then type:

quartus_sh --platform –name phylite_top_1DQS_2DQ_800MHZ

Download
Total Downloads67 (From 16 May 2016 to 13 Jun 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on May 16, 2016, 10:14 a.m.