Intel® MAX® 10 FPGA – ADC Waveform Display on LCD Design Example

Intel® MAX® 10 FPGA – ADC Waveform Display on LCD Design Example

714444
2/3/2016

Introduction

There is a high-sensitive microphone on Terasic's Intel® MAX® 10 FPGA NEEK board to receive surrounding sound. After the sound is collected and amplified approximately 392 times, it is fed into the analog-to-digital converter (ADC) of the Intel MAX 10 device. The digitized waveform will be displayed on the LCD. Meanwhile, the signal will be sent to the line-out via the audio codec and digital-to-analog converter (DAC) SMA OUT connector, both of which can be connected to an external speaker. The data will also be processed based on the volume to be displayed on the ten LEDs onboard.

Development Kit

MAX® 10 NEEK

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
Other Tags

MAX® 10 NEEK
IP Cores (4)
IP Core IP Core Category
Avalon ALTPLL ClocksPLLsResets
Altera Modular ADC core ADC
Altera Modular ADC Control core ADC
Reset Controller QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Terasic

* ACDS Version: 16.0.0 Standard


Development Kit

MAX® 10 NEEK

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
Other Tags

MAX® 10 NEEK