Design Store

Accelerated FIR with Built-In Direct Memory Access Example  

CategoryDesign Example
NameAccelerated FIR with Built-In Direct Memory Access Example
DescriptionThis design example implements a FIR filter with built-in direct memory access on a Cyclone V E FPGA Development Kit. The finite impulse response (FIR) filter is a common algorithm used in digital signal processing (DSP) systems. In this example, a FIR filter has been integrated into a single Qsys component containing Avalon® Memory-Mapped (Avalon-MM) read and write masters. The read master is responsible for supplying the filter with input data (from the SSRAM in this example), while the write master is responsible for writing the filter response back to memory (the DDR3 SDRAM in this example). Since the filter has Avalon mastering capabilities, you do not need to use a separate direct memory access (DMA) engine to accomplish the filter operation.

The purpose of this design example is to illustrate the accelerating effect of performing computationally complex operation in hardware instead of software. Furthermore, although this design performs filter operations, you can also reuse the accelerator for your own data transforms, as described in the documentation.
Operating SystemNone
IP Core
IP CoreHeading
PIO (Parallel I/O)Other
Avalon-MM Clock Crossing BridgeQsysInterconnect
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
External Memory DLL blockExternalMemoryInterfaces
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
External Memory OCT blockExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
Generic Tri-State ControllerOther
Tristate Controller AggregatorQsysInterconnect
Tristate Controller TranslatorQsysInterconnect
Tri-State Conduit BridgeQsysInterconnect
Tri-State Conduit Pin SharerQsysInterconnect
Memory-Mapped ArbiterQsysInterconnect
Tri-State Conduit Pin Sharer CoreQsysInterconnect
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Performance Counter UnitArithmetic
Altera PLLClocksPLLsResets
Interval TimerPeripherals
Version1.02
FamilyCyclone V
Device5CEFA7
Documentation
DocumentDescription
Accelerated FIR with Built-in DMA User GuideA user guide for the Cyclone V E design example "Accelerated FIR with Built-In Direct Memory Access Example" available from the Altera Design store.
Development KitCyclone V E FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/Custom_FIR_DMA.par

Once the process completes, then type:

quartus_sh --platform –name Custom_FIR_DMA

Download
Total Downloads237 (From 31 May 2016 to 13 Jun 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on April 6, 2017, 9 a.m.