Introduction
Development Kit
IP Core | IP Core Category |
---|---|
PIO (Parallel I/O) | Other |
Avalon-MM Clock Crossing Bridge | QsysInterconnect |
DDR3 SDRAM Controller with UniPHY | ExternalMemoryInterfaces |
Altera DDR3 Nextgen Memory Controller | ExternalMemoryInterfaces |
Altera Nextgen Memory Controller MM-ST Adapter | ExternalMemoryInterfaces |
Altera DDR3 Nextgen Memory Controller Core | ExternalMemoryInterfaces |
External Memory DLL block | ExternalMemoryInterfaces |
altera_jtag_avalon_master | QsysInterconnect |
Avalon-ST Bytes to Packets Converter | QsysInterconnect |
Avalon-ST Channel Adapter | QsysInterconnect |
Avalon-ST Single Clock FIFO | QsysInterconnect |
Avalon-ST JTAG Interface | QsysInterconnect |
Avalon-ST Packets to Bytes Converter | QsysInterconnect |
Reset Controller | QsysInterconnect |
Avalon-ST Timing Adapter | QsysInterconnect |
Avalon Packets to Transaction Converter | QsysInterconnect |
Altera DDR3 AFI Multiplexer | ExternalMemoryInterfaces |
MM Interconnect | QsysInterconnect |
Avalon-MM Master Translator | QsysInterconnect |
Avalon-MM Slave Translator | QsysInterconnect |
External Memory OCT block | ExternalMemoryInterfaces |
DDR3 SDRAM External Memory PHY | ExternalMemoryInterfaces |
DDR3 SDRAM External Memory PLL/DLL/OCT block | ExternalMemoryInterfaces |
DDR3 SDRAM Qsys Sequencer | ExternalMemoryInterfaces |
Avalon-MM Master Agent | QsysInterconnect |
Memory-Mapped Traffic Limiter | QsysInterconnect |
Avalon-MM Slave Agent | QsysInterconnect |
Avalon-MM Pipeline Bridge | QsysInterconnect |
Generic Tri-State Controller | Other |
Tristate Controller Aggregator | QsysInterconnect |
Tristate Controller Translator | QsysInterconnect |
Tri-State Conduit Bridge | QsysInterconnect |
Tri-State Conduit Pin Sharer | QsysInterconnect |
Memory-Mapped Arbiter | QsysInterconnect |
Tri-State Conduit Pin Sharer Core | QsysInterconnect |
IRQ Mapper | QsysInterconnect |
IRQ Clock Crosser | QsysInterconnect |
JTAG UART | ConfigurationProgramming |
Avalon-ST Adapter | QsysInterconnect |
Avalon-ST Error Adapter | QsysInterconnect |
Memory-Mapped Demultiplexer | QsysInterconnect |
Memory-Mapped Multiplexer | QsysInterconnect |
Avalon-ST Handshake Clock Crosser | QsysInterconnect |
Memory-Mapped Burst Adapter | QsysInterconnect |
Memory-Mapped Width Adapter | QsysInterconnect |
Memory-Mapped Router | QsysInterconnect |
On-Chip Memory (RAM or ROM) | OnChipMemory |
Performance Counter Unit | Arithmetic |
Altera PLL | ClocksPLLsResets |
Interval Timer | Peripherals |
Detailed Description
The finite impulse response (FIR) filter is a common algorithm used in digital signal processing (DSP) systems In this example, a FIR filter has been integrated into a single Qsys component containing Avalon Memory-Mapped (Avalon-MM) read and write masters. The read master is responsible for supplying the filter with input data (from the SSRAM in this example), while the write master is responsible for writing the filter response back to memory (the DDR3 SDRAM in this example). Since the filter has Avalon mastering capabilities, you do not need to use a separate direct memory access (DMA) engine to accomplish the filter operation.
The purpose of this design example is to illustrate the accelerating effect of performing computationally complex operation in hardware instead of software. Furthermore, although this design performs filter operations, you can also reuse the accelerator for your own data transforms, as described in the documentation.
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Note:
* ACDS Version: 16.0.0 Standard