|Name||Accelerated FIR with Built-In Direct Memory Access Example|
|Description||This design example implements a FIR filter with built-in direct memory access on a Cyclone V E FPGA Development Kit. The finite impulse response (FIR) filter is a common algorithm used in digital signal processing (DSP) systems. In this example, a FIR filter has been integrated into a single Qsys component containing Avalon® Memory-Mapped (Avalon-MM) read and write masters. The read master is responsible for supplying the filter with input data (from the SSRAM in this example), while the write master is responsible for writing the filter response back to memory (the DDR3 SDRAM in this example). Since the filter has Avalon mastering capabilities, you do not need to use a separate direct memory access (DMA) engine to accomplish the filter operation.|
The purpose of this design example is to illustrate the accelerating effect of performing computationally complex operation in hardware instead of software. Furthermore, although this design performs filter operations, you can also reuse the accelerator for your own data transforms, as described in the documentation.
|Development Kit||Cyclone V E FPGA Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
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|Total Downloads||233 (From 31 May 2016 to 06 Dec 2019)|
|Quartus Prime Version||Download Quartus Prime v16.0|
|Quartus Prime Edition||Standard|
Last updated on April 6, 2017, 9 a.m.