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Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design example  


CategoryDesign Example \ Outside Design Store
NameArria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design example
DescriptionThis basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard and enhanced PCS switching as well as TX PLL switching. The two TX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profiles. The design consist of two transceiver channels with fixed data pattern. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design will reconfigure the channels between standard and enhanced PCS. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example. The register value to write for TX PLL switching here is obtained manually through simulation. You should create your own mechanism to perform on-the-fly read-modify-write for TX PLL switching.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design exampleTransceivers
Development KitArria 10 GX FPGA Development Kit
Quartus Prime VersionDownload Quartus Prime v15.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 19, 2020, 4:30 p.m.