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1G/2.5G Ethernet Design Example for Arria V Devices  


CategoryDesign Example \ Outside Design Store
Name1G/2.5G Ethernet Design Example for Arria V Devices
DescriptionThis design example demonstrates 1G/2.5G Ethernet IP solution for Arria V® device family using Altera® Low Latency Ethernet 10G MAC (1G/2.5G mode) and 1G/2.5G/10G Multi-rate Ethernet PHY IP cores on Arria V GT FPGA Development Board with small form factor pluggable plus (SFP+).
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGTFD7
Documentation
DocumentDescription
1G/2.5G Ethernet Design Example for Arria V DevicesInterfaces
Development KitArria V GT Development Kit
Quartus Prime VersionDownload Quartus Prime v15.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 19, 2020, 4:21 p.m.