Design Store


Board Management Controller  


CategoryDesign Example
NameBoard Management Controller
DescriptionBoard management controller allow you to control PM Bus based power module.This design example using ALTERA MAX® 10 FPGA Development Kit and ALTERA Enpirion® ED810X+FDMF5820 Kit By using the MAX 10 FPGA, the design got simpler as the voltage can be read back by the built in ADC in MAX 10. Customize your controller by using NIOS II.
Operating SystemNone
IP Core
IP CoreHeading
IRQ MapperQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Altera Modular Dual ADC coreADC
Altera Modular ADC command_in Splitter coreADC
Altera Modular ADC Control coreADC
Altera Modular ADC Dual Sync coreADC
Altera Modular ADC Response Merge coreADC
Altera Modular ADC Sample Storage coreADC
Altera Modular ADC Sequencer coreADC
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
Altera On-Chip FlashFlash
On-Chip Memory (RAM or ROM)OnChipMemory
PIO (Parallel I/O)Other
Reset ControllerQsysInterconnect
Avalon ALTPLLClocksPLLsResets
UART (RS-232 Serial Port)Other
Interval TimerPeripherals
Version1.00
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
AN761-Board Management ControllerThe example design shows how to use a MAX 10 device as a board management controller for power-up sequencing of a typical system using the Power Management BUS (PMBus™) interface.
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/bmc.par

Once the process completes, then type:

quartus_sh --platform –name bmc

Download   (The download link will expire on Feb. 28, 2021, 2:50 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.1
Quartus Prime EditionStandard
VendorIntel


Last updated on May 10, 2016, 12:29 a.m.