Design Store


MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example  


CategoryDesign Example
NameMAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example
DescriptionThis design example demonstrates Triple Speed Ethernet IP solution for MAX 10® device family using Altera® Triple Speed Ethernet MAC and Marvell 88E1111 PHY chip on MAX 10 FPGA Development Kit. It provides flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks. In this design, the Single-Port Triple-Speed Ethernet MAC connects to the on-board PHY chip through the Reduce Gigabit Media Independent Interface (RGMII).
Operating SystemNone
IP Core
IP CoreHeading
ALTCLKCTRLClocksPLLsResets
Altera GPIO LiteOther
Avalon ALTPLLClocksPLLsResets
Avalon-ST AdapterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Triple-Speed EthernetEthernet
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User GuideMAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/max10tse.par

Once the process completes, then type:

quartus_sh --platform –name max10tse

Download   (The download link will expire on Jan. 26, 2022, 2:28 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.1
Quartus Prime EditionStandard
VendorIntel

Last updated on Jan. 21, 2016, 9:43 p.m.