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JPEG Decoder Design Example (OpenCL)  


CategoryDesign Example \ Outside Design Store
Name JPEG Decoder Design Example (OpenCL)
DescriptionThis design example implements a high-performance JPEG decoder using Open Computing Language (OpenCLTM). The solution consists of several OpenCL kernels connected via Altera’s channels vendor extension, where each kernel performs one step in the JPEG decoding pipeline (e.g. Huffman decoding, inverse DCT).

This implementation can decode JPEG images at a rate of 2.6 MBps, which enables saturation of a PCI Express® (PCIe®) Gen2x8 link for transferring the decoded image back to the host memory.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGSED6
Documentation
DocumentDescription
JPEG Decoder Design Example (OpenCL)-
Development KitNon kit specific Stratix V Design Examples
Quartus Prime VersionDownload Quartus Prime v15.1
Quartus Prime EditionStandard
VendorIntel

Last updated on May 31, 2016, 8:53 p.m.