Design Store


RSU over PCIe Design Example  


CategoryDesign Example
NameRSU over PCIe Design Example
DescriptionThe RSU over PCIe design example is target to demonstrate a method to use PC to download program files to EPCQ, and control Remote Update IP to achieve FPGA reconfiguration with the downloaded program files.
Operating SystemNone
IP Core
IP CoreHeading
Transceiver Reconfiguration ControllerTransceiverPHY
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Reset ControllerQsysInterconnect
Altera Serial Flash ControllerFlash
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Modular Scatter-Gather DMABridgesAndAdaptors
Modular SGDMA DispatcherBridgesAndAdaptors
Read MasterQsysInterconnect
Write MasterQsysInterconnect
Avalon-MM Stratix V Hard IP for PCI ExpressPCIExpress
Altera PLLClocksPLLsResets
Altera Remote UpdateConfigurationProgramming
Altera Remote Update CoreConfigurationProgramming
Version1.0
FamilyStratix V
Device5SGXEA7
Documentation
DocumentDescription
RSU over PCIe Design Example-
Development KitStratix V GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/RSU_over_PCIe_Design_Example.par

Once the process completes, then type:

quartus_sh --platform –name RSU_over_PCIe_Design_Example

Download   (The download link will expire on April 17, 2021, 8:49 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel

Last updated on Jan. 21, 2016, 9:39 p.m.