Design Store


Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design  


CategoryDesign Example
NameArria 10 JESD204B AD9144-AD9625 Interoperability Reference Design
DescriptionThe reference design showcases Altera JESD204B IP core interoperates with ADI AD9144 DAC and AD9625 ADC with NIOS II Gen2 as the control unit
Operating SystemBareMetal
IP Core
IP CoreHeading
Altera IOPLLClocksPLLsResets
Altera PLL ReconfigClocksPLLsResets
IRQ MapperQsysInterconnect
Jesd204bJESD204B
Jesd204b PHY wrapperJESD204B
Arria 10 Transceiver Native PHYTransceiverPHY
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
NCODSP
Reset SequencerQsysInterconnect
Reset ControllerQsysInterconnect
Arria 10 Transceiver ATX PLLTransceiverPLL
Transceiver PHY Reset ControllerTransceiverPHY
Avalon-ST SplitterQsysInterconnect
JTAG UARTConfigurationProgramming
On-Chip Memory (RAM or ROM)OnChipMemory
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
PIO (Parallel I/O)Other
Interval TimerPeripherals
SPI (3 Wire Serial)SPI
Altera GPIOOther
Altera GPIO CoreOther
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design User GuideUser guide for Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/a10gx_jesd204b_ad9144_ad9625_nios_ed.par

Once the process completes, then type:

quartus_sh --platform –name a10gx_jesd204b_ad9144_ad9625_nios_ed

Download
Total Downloads115 (From 05 Oct 2015 to 19 Nov 2019)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


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Last updated on Dec. 29, 2015, 2:48 p.m.