Design Store


Remote System Debug  


CategoryDesign Example
NameRemote System Debug
DescriptionAltera offers an integrated set of System Level Debug (SLD) tools, e.g. SignalTap II Logic Analyzer. Historically, SLD communication solution was based on the Altera JTAG Interface (AJI) which interfaced with the outside world through the JTAG. This example interface the SLD to the outside world directly through Ethernet, without using the USB Blaster. It handle the network stack on the HPS of Altera SoC.
Operating SystemLinux
IP Core
IP CoreHeading
Altera In-System Sources & ProbesSimulationDebugVerification
Arria 10 Hard Processor SystemHardProcessorComponents
PIO (Parallel I/O)Other
Arria 10 External Memory Interfaces for HPSExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
UART (RS-232 Serial Port)Other
Reset ControllerQsysInterconnect
JTAG to Avalon Master BridgeConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Altera Interrupt Latency CounterOther
IRQ MapperQsysInterconnect
AXI TranslatorHardProcessorComponents
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
AXI Master AgentHardProcessorComponents
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
AXI Slave AgentHardProcessorComponents
On-Chip Memory (RAM or ROM)OnChipMemory
Avalon-MM Pipeline BridgeQsysInterconnect
SLD Hub Controller SystemSimulationDebugVerification
Avalon ST Debug FabricQsysInterconnect
Avalon-ST DemultiplexerQsysInterconnect
Altera Management Reset BlockOther
Avalon-ST MultiplexerQsysInterconnect
SLD Hub ControllerSimulationDebugVerification
altera_streaming_sld_hub_controller_coreQsysInterconnect
Avalon-MM Debug LinkQsysInterconnect
altera_connection_identification_rom_wrapperQsysInterconnect
altera_mm_mgmt_wrapperQsysInterconnect
Avalon FIFO MemoryOnChipMemory
System ID PeripheralOther
altera_arria10_hps_ioOther
altera_jtag_avalon_masterQsysInterconnect
Version1.0
FamilyArria 10
Device10AS066
Documentation
DocumentDescription
Link to RocketBoards-
Development KitArria 10 SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel

Last updated on Oct. 7, 2015, 9:14 a.m.