Design Store

SPI Slave to Avalon Master Bridge  

CategoryDesign Example
NameSPI Slave to Avalon Master Bridge
DescriptionThis design example demonstrates how to use the SPI Slave to Avalon
Master Bridge to provide a connection between the host and the remote system
for SPI transactions. This design is a modified version of Altera's original

The hardware system in this design consists of two Qsys sub-systems. The first
is the host system, which consists of a Nios II CPU and SPI Master Core, that
initiates the SPI transactions. One new feature is that the Nios CPU executes
code from internal user flash. This setup is new with Max 10. The second is the remote system which
consists of the SPI Slave to Avalon Master Bridge, an on-chip memory, and
connection to the Odyssey board's LEDs and Switch. For demonstration purposes,
these two sub-systems are connected internally within the FPGA without going
through any physical pin routing.

The software portion demonstrates how to perform read and write transactions
using the SPI Slave to Avalon Master Bridge. In order for the SPI Slave to
Avalon Master Bridge to successfully convert incoming streams of data into
Avalon Memory-Mapped (Avalon-MM) transactions, the host system CPU needs to
encode and packetize the streams of data according to the protocols used by
the bridge. Similarly, outgoing streams of data from the SPI Slave to the
Avalon Master Bridge need to be converted according to the same protocol used
by the CPU.
Operating SystemBareMetal
IP Core
IP CoreHeading
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
PIO (Parallel I/O)Other
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
Altera On-Chip FlashFlash
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
SPI (3 Wire Serial)SPI
Memory-Mapped Traffic LimiterQsysInterconnect
SPI Slave to Avalon Master BridgeSPI
FamilyMAX 10
Original SPI Slave to Avalon Master BridgeLink to the original design example targeting Cyclone III
Development KitOdyssey MAX 10 FPGA Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/spi_bridge.par

Once the process completes, then type:

quartus_sh --platform –name spi_bridge

Download   (The download link will expire on Oct. 22, 2021, 1:29 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorMacnica Americas

Last updated on Nov. 30, 2015, 2:29 p.m.