|Name||SPI Slave to Avalon Master Bridge|
|Description||This design example demonstrates how to use the SPI Slave to Avalon |
Master Bridge to provide a connection between the host and the remote system
for SPI transactions. This design is a modified version of Altera's original
The hardware system in this design consists of two Qsys sub-systems. The first
is the host system, which consists of a Nios II CPU and SPI Master Core, that
initiates the SPI transactions. One new feature is that the Nios CPU executes
code from internal user flash. This setup is new with Max 10. The second is the remote system which
consists of the SPI Slave to Avalon Master Bridge, an on-chip memory, and
connection to the Odyssey board's LEDs and Switch. For demonstration purposes,
these two sub-systems are connected internally within the FPGA without going
through any physical pin routing.
The software portion demonstrates how to perform read and write transactions
using the SPI Slave to Avalon Master Bridge. In order for the SPI Slave to
Avalon Master Bridge to successfully convert incoming streams of data into
Avalon Memory-Mapped (Avalon-MM) transactions, the host system CPU needs to
encode and packetize the streams of data according to the protocols used by
the bridge. Similarly, outgoing streams of data from the SPI Slave to the
Avalon Master Bridge need to be converted according to the same protocol used
by the CPU.
|Development Kit||Odyssey MAX 10 FPGA Kit|
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Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
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|Quartus Prime Version||Download Quartus Prime v15.0|
|Quartus Prime Edition||Standard|
Last updated on Nov. 30, 2015, 2:29 p.m.