Design Store


QSPI XIP reference design  


CategoryDesign Example
NameQSPI XIP reference design
DescriptionThis QSPI XIP reference design demonstrates the following items:
1\ Boot from QSPI: In Industrial applications, for example servo drives, can save board space by using the QSPI flash for program code
2\ Preload a portion of QSPI execution/read only data window to L2 cache and lock it to save execution time.
Operating SystemBareMetal
IP Core
IP CoreHeading
PIO (Parallel I/O)Other
JTAG to Avalon Master BridgeConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Arria V/Cyclone V Hard Processor SystemHardProcessorComponents
Altera Interrupt Latency CounterOther
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
AXI Master AgentHardProcessorComponents
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
AXI Slave AgentHardProcessorComponents
On-Chip Memory (RAM or ROM)OnChipMemory
System ID PeripheralOther
altera_jtag_avalon_masterQsysInterconnect
altera_hps_ioHardProcessorComponents
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
XIP_demo.docDocument of QSPI XIP reference design
Development KitCyclone V SoC Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/soc_system_qspi_new.par

Once the process completes, then type:

quartus_sh --platform –name soc_system_qspi_new

Download   (The download link will expire on Oct. 21, 2021, 11:31 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Nov. 3, 2015, 5:54 p.m.