|Name||Nios II + Qsys "Hello World" Lab|
|Description||This step by step lab shows a user how to build a Nios II Qsys based system that includes GPIO, UART and on-chip memory. This lab requires the MAX 10 Development Kit from Altera. The appendix B in the lab manual describes how to combine the SW image with the HW .sof file.|
|Development Kit||MAX 10 FPGA Development Kit|
Download (The download link will expire on Oct. 31, 2020, 1:20 a.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v15.0|
|Quartus Prime Edition||Standard|
Last updated on Aug. 28, 2015, 5:15 p.m.