Design Store


Nios II + Qsys "Hello World" Lab  


CategoryTutorial
NameNios II + Qsys "Hello World" Lab
DescriptionThis step by step lab shows a user how to build a Nios II Qsys based system that includes GPIO, UART and on-chip memory. This lab requires the MAX 10 Development Kit from Altera. The appendix B in the lab manual describes how to combine the SW image with the HW .sof file.
Operating SystemBareMetal
IP Core
IP CoreHeading
IRQ MapperQsysInterconnect
PIO (Parallel I/O)Other
MM InterconnectQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
JTAG UARTConfigurationProgramming
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Nios II + Qsys Hello World Lab ManualThis lab describes how to build a small Nios II system with processor, UART, GPIO and onchip memory on the MAX 10 Development Kit from Altera. You will develop software to display "hello world" on a terminal and use the GPIO to interface between push button switches and LEDs.The included design download is for the solution, but as a starting point you only need the lab manual.
Nios II Hardware Development Online Training ClassFree Nios II Hardware Online Training
Nios II Software Development Online Training ClassFree Nios II Software Online Training
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/hello_world_lab.par

Once the process completes, then type:

quartus_sh --platform –name hello_world_lab

Download   (The download link will expire on Oct. 31, 2020, 1:20 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 28, 2015, 5:15 p.m.