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MAX10 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART with Linux  


CategoryDesign Example
NameMAX10 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART with Linux
DescriptionThis is the Golden Hardware Reference Design (GHRD) for Altera MAX 10 FPGA Development Kit.

The GHRD is an important part of the Golden System Reference Design (GSRD) and consists of the following components:
- Nios II Gen2 Processor with memory management unit (MMU) enabled
- DDR3 SDRAM controller
- Quad SPI controller
- RGMII Gigabit Ethernet
- Modular SGDMA
- UART
- PIO access to button and LED
- System Clock
- On-chip memory
- System ID
- JTAG for debugging purposes

This design by default has Rev C pinout in the Pin Planner. If you would like to change the pinout to Rev B, go to Tools -> Tcl Scripts and select RevC_to_RevB.tcl and hit Run.
If you want to go back to Rev C, you can execute RevB_to_RevC.tcl pinout.
To find out the Revision of your board, look at the back of the board towards the bottom center. You can also refer to the image on design store.
Operating SystemLinux
IP Core
IP CoreHeading
ALTCLKCTRLClocksPLLsResets
Altera GPIO LiteOther
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Avalon ALTPLLClocksPLLsResets
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
Altera SOFT ASMIBLOCKOther
Altera Interrupt Latency CounterOther
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Triple-Speed EthernetEthernet
Modular Scatter-Gather DMABridgesAndAdaptors
Modular SGDMA DispatcherBridgesAndAdaptors
Write MasterQsysInterconnect
Read MasterQsysInterconnect
Reset ControllerQsysInterconnect
Interval TimerPeripherals
System ID PeripheralOther
JTAG to Avalon Master BridgeConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
UART (RS-232 Serial Port)Other
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Altera MAX10 10M50 Rev C Development Kit Linux SetupThis page provides information about running Nios II Linux on Altera MAX10 10M50 Rev C development kit.
Development KitMAX 10 FPGA Development Kit
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 31, 2015, 5:03 p.m.