|Name||MAX10 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART with Linux|
|Description||This is the Golden Hardware Reference Design (GHRD) for Altera MAX 10 FPGA Development Kit.|
The GHRD is an important part of the Golden System Reference Design (GSRD) and consists of the following components:
- Nios II Gen2 Processor with memory management unit (MMU) enabled
- DDR3 SDRAM controller
- Quad SPI controller
- RGMII Gigabit Ethernet
- Modular SGDMA
- PIO access to button and LED
- System Clock
- On-chip memory
- System ID
- JTAG for debugging purposes
This design by default has Rev C pinout in the Pin Planner. If you would like to change the pinout to Rev B, go to Tools -> Tcl Scripts and select RevC_to_RevB.tcl and hit Run.
If you want to go back to Rev C, you can execute RevB_to_RevC.tcl pinout.
To find out the Revision of your board, look at the back of the board towards the bottom center. You can also refer to the image on design store.
|Development Kit||MAX 10 FPGA Development Kit|
|Quartus Prime Version||Download Quartus Prime v15.0|
|Quartus Prime Edition||Standard|
Last updated on Aug. 31, 2015, 5:03 p.m.