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DECA Graphics Design Example  

CategoryDesign Example
NameDECA Graphics Design Example
DescriptionThis design implements frame buffer based graphics on Altera MAX10 Arrow/Terasic DECA board in VIP (Video and Image Processing Suite).
Operating SystemLinux
IP Core
IP CoreHeading
Frame ReaderOther
Avalon ALTPLLClocksPLLsResets
PIO (Parallel I/O)Other
Clocked Video Output II (4K Ready)AudioVideo
CVO schedulerOther
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
MM InterconnectQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
System ID PeripheralOther
Interval TimerPeripherals
Test Pattern Generator II (4K Ready)Other
Mixer II (4K Ready)AudioVideo
FamilyMAX 10
Link to
Development KitArrow MAX 10 DECA
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard

Last updated on Nov. 6, 2016, 10:11 p.m.