Design Store


BMS Battery Management System Reference Design (AN762)  


CategoryDesign Example
NameBMS Battery Management System Reference Design (AN762)
DescriptionThe Altera® Battery Management System (BMS) reference design demonstrates battery State Of Charge (SOC) estimation in an FPGA-based real-time control platform that could be extended to include other BMS functionality such as battery State-of-Health monitoring and charge equalization (cell balancing). It uses a Dual Extended Kalman Filter (DEKF) algorithm to estimate SOC values for 96 cells, using a MAX® 10 development kit. The reference design’s System-in-the-Loop simulation runs under MATLAB®/Simulink®.
Operating SystemNone
IP Core
IP CoreHeading
Avalon ALTPLLClocksPLLsResets
Avalon-MM Clock Crossing BridgeQsysInterconnect
IRQ MapperQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
JTAG UARTConfigurationProgramming
On-Chip Memory (RAM or ROM)OnChipMemory
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Custom Instruction Slave TranslatorQsysInterconnect
Custom Instruction InterconnectQsysInterconnect
Custom Instruction Master TranslatorQsysInterconnect
Floating Point Hardware 2Arithmetic
Floating Point Hardware 2 CombinatorialArithmetic
Floating Point Hardware 2 Multi-cycleArithmetic
Performance Counter UnitArithmetic
System ID PeripheralOther
Interval TimerPeripherals
Version15.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Battery Management System Reference Design-
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/bms_soc_max10m50.par

Once the process completes, then type:

quartus_sh --platform –name bms_soc_max10m50

Download   (The download link will expire on May 11, 2021, 4:26 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on May 3, 2016, 4:05 p.m.