|Name||Arria 10 Single-Port Triple-Speed Ethernet and On-Board PHY Chip Design|
|Description||This reference design describes a Single-Port Triple-Speed Ethernet and On-Board PHY Chip design that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore® functions (10/100/1000 MAC+SGMII PCS+LVDS variant) with on-board Marvell 88E1111 PHY chips targeted on Altera Arria 10 FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations using system loopbacks.|
The reference designs offer the following features:
■ Support programmable test parameters such as number of packets, packet length, source and destination MAC addresses, and payload-data type.
■ Support testing with sequential random bursts, which enables the configuration of each burst for the number of packets, payload-data type, and payload size. A pseudo-random binary sequence (PRBS) generator generates the payload data type in fixed incremental values or in a random sequence.
■ Demonstrate transmission and reception of Ethernet packets through internal loopback path at the maximum theoretical data rates without errors.
■ Supports System Console user interface. This user interface, which is based on Tcl allows user to dynamically configure, debug, and test the reference designs.
|Development Kit||Arria 10 GX FPGA Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v15.0|
|Quartus Prime Edition||Standard|
Last updated on Oct. 8, 2015, 2:13 p.m.