Design Store


Arria 10 Single-Port Triple-Speed Ethernet and On-Board PHY Chip Design   


CategoryDesign Example
NameArria 10 Single-Port Triple-Speed Ethernet and On-Board PHY Chip Design
DescriptionThis reference design describes a Single-Port Triple-Speed Ethernet and On-Board PHY Chip design that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore® functions (10/100/1000 MAC+SGMII PCS+LVDS variant) with on-board Marvell 88E1111 PHY chips targeted on Altera Arria 10 FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations using system loopbacks.


The reference designs offer the following features:
■ Support programmable test parameters such as number of packets, packet length, source and destination MAC addresses, and payload-data type.
■ Support testing with sequential random bursts, which enables the configuration of each burst for the number of packets, payload-data type, and payload size. A pseudo-random binary sequence (PRBS) generator generates the payload data type in fixed incremental values or in a random sequence.
■ Demonstrate transmission and reception of Ethernet packets through internal loopback path at the maximum theoretical data rates without errors.
■ Supports System Console user interface. This user interface, which is based on Tcl allows user to dynamically configure, debug, and test the reference designs.
Operating SystemNone
IP Core
IP CoreHeading
Triple-Speed EthernetEthernet
Altera LVDS SERDESOther
Reset ControllerQsysInterconnect
JTAG to Avalon Master BridgeConfigurationProgramming
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Arria 10 FPLLClocksPLLsResets
Avalon-ST AdapterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
altera_lvds_core20Other
altera_jtag_avalon_masterQsysInterconnect
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 Single-Port Triple-Speed Ethernet and On-Board PHY Chip Design User GuideThis is a A10 design migrated from AN647 design. For more information ,please refer to AN647.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/A10_MAC_PCS_LVDS.par

Once the process completes, then type:

quartus_sh --platform –name A10_MAC_PCS_LVDS

Download   (The download link will expire on April 17, 2021, 8:36 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel

Image 1

Last updated on Oct. 8, 2015, 2:13 p.m.