Design Store


AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions - Arria V  


CategoryDesign Example \ Outside Design Store
NameAN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions - Arria V
DescriptionYou can use the 28-nm devices (Arria® V, Cyclone® V, and Stratix® V device families) to implement fractional phase-locked loop (PLL) reconfiguration and dynamic phase shift for fractional PLLs with the Altera PLL and Altera PLL Reconfig IP cores in the Quartus® II software. Fractional PLLs use divide counters and different voltage-controlled oscillator (VCO) taps to perform frequency synthesis and phase shifts. For example, you can reconfigure the counter settings and dynamically phase-shift the fractional PLL (fPLL) output clock in the PLLs of 28-nm devices. You can also change the charge pump and loop filter components, which dynamically affect the fractional PLL bandwidth. You can use these fPLL components to update the clock frequency, fPLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGTFC7
Documentation
DocumentDescription
Document-
Development KitNon kit specific Arria V Design Examples
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on July 1, 2016, 2:21 p.m.