Design Store


AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Arria V  


CategoryDesign Example \ Outside Design Store
NameAN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Arria V
DescriptionThe Single-Port Triple-Speed Ethernet and On-Board PHY Chip reference designs provide flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks. The Single-Port Triple-Speed Ethernet and On-Board PHY Chip reference designs demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet IP core with on-board Marvell 88E1111 PHY chips. In these reference designs, the Triple-Speed Ethernet IP core connects to the on-board PHY chip through either the Reduce Gigabit Media Independent Interface (RGMII) or the Serial Gigabit Media Independent Interface (SGMII). The reference designs offer the following features: • Minimal hardware requirement for a complete test. • Implementation of one Triple-Speed Ethernet IP core instance supporting 10/100/1000-Mbps Ethernets operations with RGMII or SGMII with auto-negotiation. • Support for programmable test parameters such as number of packets, packet length, source and destination MAC addresses, and payload-data type. • Support for sequential random bursts test that enables the configuration of each burst for the number of packets, payload-data type, and payload size. • Demonstration of Ethernet packets transmission and reception through internal loopback path at the maximum theoretical data rates without errors. • Support for gathering throughput statistics. • Support for System Console user interface.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGXFB3
Documentation
DocumentDescription
Document-
Development KitArria V GX Starter Kit
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on July 1, 2016, 2:42 p.m.