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AN 756: Altera GPIO to Altera PHYLite Design Implementing Guidelines  


CategoryDesign Example \ Outside Design Store
NameAN 756: Altera GPIO to Altera PHYLite Design Implementing Guidelines
DescriptionThis Application Note describes the overview concept of IEEE 1588v2 standard and Precision Time Protocol as well as the procedure and architecture of Altera 1588 system solution reference design using Altera Arria V SoC, 10G Ethernet MAC with 10G BASE-R PHY hardware IP and software stack which is build based on Linux kernel v3.16, consists of PTP stack LinuxPTP v1.5, a preloader, 10G-bps Ethernet MAC driver and a PTP driver. The objectives of the reference design include the following: • 6.99ns timestamp accuracy using Altera 1588 hardware IP and Linux PTP software stack for 10Gbps speed. • Offset adjustment capability from the system perspective for an ordinary clock (OC) in slave mode. • Altera 1588 IP usability from the Linux system perspective for an ordinary clock in master mode. This reference design includes hardware system design and software stack which allow you to: • Perceive the usability of the hardware IP from various perspectives of the system solution. • Assess the accuracy requirements in relation to the capability of this reference design. • Replace the existing Linux PTP application with other PTP applications.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5ASTFD5
Documentation
DocumentDescription
Document-
Development KitArria V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v15.0
Quartus Prime EditionStandard
VendorIntel


Last updated on June 13, 2016, 7:59 p.m.