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Cyclone V SoC SDRAM Performance Example Design  


CategoryDesign Example \ Linux Outside Design Store
NameCyclone V SoC SDRAM Performance Example Design
DescriptionThis example design showcases the SoC multi-port front end of the SDRAM controller. None User-Space applications are included for displaying and adjusted MPFE port priorities and weights. Hardware IP components for monitoring AXI transactions and for generating AXI traffic are also included
Operating SystemLinux
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
Cyclone V SoC SDRAM Performance Example DesignRocketboards
Development KitCyclone V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v14.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Oct. 5, 2017, 1:53 p.m.