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CycloneV SGMII Example Design  


CategoryDesign Example
NameCycloneV SGMII Example Design
DescriptionDesign Example demonstrates how you can route the HPS EMAC into the FPGA in order to use FPGA I/O for the interface
Operating SystemLinux
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
CycloneV SGMII Example DesignRocketboards
Development KitCyclone V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v14.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Oct. 24, 2017, 7:46 p.m.