Design Store


Datamover Design Example  


CategoryDesign Example
NameDatamover Design Example
DescriptionThe Datamover example design uses a Cyclone V SoC development kit to demonstrate data communication between the FPGA logic and SDRAM controlled through the Hard Processor System (HPS) portion of the device. The design uses a Nios II processor along with an mSGDMA in the FPGA fabric to move data through the F2H bridge. The Nios II is also used to track the time for each DMA transfer as well as the loop time, which is defined as the total duration for a packet to enter the SoC, be processed, and then transferred into on-chip memory in the FPGA fabric. The jitter of each measurement, ingress DMA time, and egress DMA time are also calculated.

The software for this design is discussed with respect to implementation using Linux with core affinity, VxWorks with core affinity, and a baremetal solution using hardware libs. All three software implementations yield different results and statistics that can assist a user in deciding the best software solution to meet the real-time requirements of a design.
Operating SystemLinux
IP Core
IP CoreHeading
EPCS/EPCQx1 Serial Flash ControllerFlash
Arria V/Cyclone V Hard Processor SystemHardProcessorComponents
Altera Interrupt Latency CounterOther
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
Altera Avalon Mailbox (simple)QsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
AXI Master AgentHardProcessorComponents
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
AXI Slave AgentHardProcessorComponents
Modular Scatter-Gather DMABridgesAndAdaptors
Modular SGDMA DispatcherBridgesAndAdaptors
Read MasterQsysInterconnect
Write MasterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Performance Counter UnitArithmetic
PIO (Parallel I/O)Other
Altera PLLClocksPLLsResets
Reset ControllerQsysInterconnect
System ID PeripheralOther
altera_hps_ioHardProcessorComponents
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
Link to RocketBoards-
Development KitCyclone V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v14.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Oct. 7, 2015, 9:03 a.m.