|Category||Design Example \ Outside Design Store|
|Name||AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface|
|Description||The Altera SoC integrates an ARM® Cortex®-A9-based hard processor system (HPS) consisting of|
processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect
backbone. The Cyclone V® HPS Interface provides up to 67 I/O pins to share with multiple peripherals
through sets of configurable multiplexers. The Arria V Interface provides up to 71 I/O pins.
This application note describes the steps required to route an HPS peripheral through the FPGA interface
using Qsys and Quartus II software. A simple design example is included to demonstrate exporting HPS
EMAC0 and I2C0 peripheral signals to the FPGA interface using a Cyclone V SoC Development Kit.
|Development Kit||Cyclone V SoC Development Kit|
|Quartus Prime Version||Download Quartus Prime v14.0|
|Quartus Prime Edition||Standard|
Last updated on June 13, 2016, 11:43 a.m.