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AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface  


CategoryDesign Example \ Outside Design Store
NameAN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
DescriptionThe Altera SoC integrates an ARM® Cortex®-A9-based hard processor system (HPS) consisting of
processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect
backbone. The Cyclone V® HPS Interface provides up to 67 I/O pins to share with multiple peripherals
through sets of configurable multiplexers. The Arria V Interface provides up to 71 I/O pins.
This application note describes the steps required to route an HPS peripheral through the FPGA interface
using Qsys and Quartus II software. A simple design example is included to demonstrate exporting HPS
EMAC0 and I2C0 peripheral signals to the FPGA interface using a Cyclone V SoC Development Kit.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
Documentation-
Development KitCyclone V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v14.0
Quartus Prime EditionStandard
VendorIntel


Last updated on June 13, 2016, 11:43 a.m.