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AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller for Arria V  


CategoryDesign Example \ Outside Design Store
NameAN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller for Arria V
DescriptionThe Arria V® and Cyclone V Hard Processor System (HPS) provide two USB On-the-Go (OTG) controllers.
Each USB 2.0 OTG controller supports a single USB port connected through a USB 2.0 Transceiver
Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) compliant PHY.
When interfacing your design to a USB PHY, it is important to do timing analysis to ensure that the
interface between the USB controller and USB PHY works reliably across a range of process, voltage and
temperature (PVT) variations.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGTFC7
Documentation
DocumentDescription
Documentation-
Development KitNon kit specific Arria V Design Examples
Quartus Prime VersionDownload Quartus Prime v14.0
Quartus Prime EditionStandard
VendorIntel


Last updated on June 13, 2016, 11:43 a.m.