Design Store


AN 456: PCI Express High Performance Reference Design for Cyclone V FPGA  


CategoryDesign Example \ Outside Design Store
NameAN 456: PCI Express High Performance Reference Design for Cyclone V FPGA
DescriptionThe PCI Express High-Performance Reference Design highlights the performance of the Altera’s PCI
Express®
products. The design includes a high-performance chaining direct memory access (DMA) that
transfers data between the a PCIe Endpoint in the FPGA, internal memory and the system memory. The
reference design includes a Windows-based software application that sets up the DMA transfers. The
software application also measures and displays the performance achieved for the transfers. This reference
design enables you to evaluate the performance of the PCI Express protocol in the following devices:
• Arria II GX
• Arria V
• Arria 10
• Cyclone IV GX
• Cyclone V
• Stratix IV GX
• Stratix V
Altera offers the IP Compiler for PCI Express IP core in both hard IP and soft IP implementations, and
the Arria V, Arria 10, Cyclone V, and Stratix V Hard IP for PCI Express in hard IP. The hard IP
implementation is available as a Root Port or Endpoint. Depending on the device used, the hard IP
implementation is compliant with PCI Express Base Specification 1.1, 2.0, or 3.0. The soft IP implementa‐
tion is available only as an Endpoint. It is compliant with PCI Express Base Specification 1.0a or 1.1.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CEBA2
Documentation
DocumentDescription
Documentation-
Development KitNon kit specific Cyclone V Design Examples
Quartus Prime VersionDownload Quartus Prime v14.0
Quartus Prime EditionStandard
VendorIntel


Last updated on June 13, 2016, 11:39 a.m.