PCIe in-simulation status debug for PIPE interface
|Design Example \ Outside Design Store|
|PCIe in-simulation status debug for PIPE interface|
|This article demonstrates how to create post simulation status flags for PCIe transaction/error messages on the PIPE interface. This will be helpful for those who would like to debug the TLP and any issues associated with it. The user can simply look at the status flags and know the type of transaction done by the TLP without actually having to decode it. The current files are known to be compatible with the Modelsim simulator and Synopsys VCS (with limitations) and support all Gen1 and Gen2 PCIe HIP configurations from Altera.|
|Non kit specific Stratix V Design Examples|
|Download Quartus Prime v13.1|
Last updated on Aug. 20, 2020, 5:14 p.m.