|Name||Device Wide AMP|
|Description||A heterogeneous Asymmetric Multi Processing (AMP) example design that is composed of the following:|
HPS domain: ARM Cortex-A9 running Linux SMP
FPGA domain: Nios-II running uC/OS-II
The HPS domain is intended for non-real-time processing, while the FPGA domain is intended to be used for real-time processing. The communication between HPS and FPGA domains is accomplished through a MCAPI transport layer, that uses shared HPS DDR memory as underlying mechanism. FPGA domain has its own memories (OCRAM and DDRAM) so that the HPS impact on the real-time processing is minimized. With the dual domain implementation, memory access latency can be better controlled and deterministic. There are no shared peripherals between HPS and Nios-II.
A simple “hello” application is used to demonstrate the inter-processor communication for this example design. ARM Cortex-A9 sends “hello” message to Nios-II continuously and vice versa. The “hello” message received by HPS will be displayed on HPS UART; while the message received by Nios-II will be displayed on JTAG UART.
The purpose of this design example is to provide a foundation on which a custom system can be built.
|Development Kit||Cyclone V SoC Development Kit|
|Quartus Prime Version||Download Quartus Prime v13.1|
|Quartus Prime Edition||Standard|
Last updated on Oct. 7, 2015, 9:05 a.m.