Design Store


Device Wide AMP  


CategoryDesign Example
NameDevice Wide AMP
DescriptionA heterogeneous Asymmetric Multi Processing (AMP) example design that is composed of the following:
HPS domain: ARM Cortex-A9 running Linux SMP
FPGA domain: Nios-II running uC/OS-II

The HPS domain is intended for non-real-time processing, while the FPGA domain is intended to be used for real-time processing. The communication between HPS and FPGA domains is accomplished through a MCAPI transport layer, that uses shared HPS DDR memory as underlying mechanism. FPGA domain has its own memories (OCRAM and DDRAM) so that the HPS impact on the real-time processing is minimized. With the dual domain implementation, memory access latency can be better controlled and deterministic. There are no shared peripherals between HPS and Nios-II.

A simple “hello” application is used to demonstrate the inter-processor communication for this example design. ARM Cortex-A9 sends “hello” message to Nios-II continuously and vice versa. The “hello” message received by HPS will be displayed on HPS UART; while the message received by Nios-II will be displayed on JTAG UART.

The purpose of this design example is to provide a foundation on which a custom system can be built.
Operating SystemLinux
IP Core
IP CoreHeading
Address Span ExtenderQsysInterconnect
PIO (Parallel I/O)Other
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Hard Memory ControllerExternalMemoryInterfaces
External Memory DLL blockExternalMemoryInterfaces
External Memory OCT blockExternalMemoryInterfaces
DDR3 SDRAM External Memory Hard PHY CoreExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
JTAG to Avalon Master BridgeConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
EPCS/EPCQx1 Serial Flash ControllerFlash
Arria V/Cyclone V Hard Processor SystemHardProcessorComponents
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
Altera Avalon Mailbox (simple)QsysInterconnect
MM InterconnectQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
AXI Master AgentHardProcessorComponents
AXI Slave AgentHardProcessorComponents
Altera Avalon MutexQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
System ID PeripheralOther
Interval TimerPeripherals
altera_jtag_avalon_masterQsysInterconnect
altera_hps_ioHardProcessorComponents
Version1.0
FamilyCyclone V
Device5CSXFC6
Documentation
DocumentDescription
Link to RocketBoards.org-
Development KitCyclone V SoC Development Kit
Quartus Prime VersionDownload Quartus Prime v13.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Oct. 7, 2015, 9:05 a.m.