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AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core - Arria V  


CategoryDesign Example \ Outside Design Store
NameAN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core - Arria V
DescriptionThis application note describes the implementation of a deterministic latency PHY that complies with the Common Public Radio Interface (CPRI) protocol for a 6144 Mbps CPRI design in Altera® Arria® V, Cyclone® V, and Stratix® V devices with transceivers. It also describes the transceiver configuration and clocking scheme to achieve the deterministic latency functional mode.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGTFC7
Documentation
DocumentDescription
Document-
Development KitNon kit specific Arria V Design Examples
Quartus Prime VersionDownload Quartus Prime v13.0
Quartus Prime EditionStandard
VendorIntel


Last updated on July 1, 2016, 1:56 p.m.