Design Store


40Gbps Ethernet MACPHY IP Pause Control Demo Design  


CategoryDesign Example \ Outside Design Store
Name40Gbps Ethernet MACPHY IP Pause Control Demo Design
DescriptionThis reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GT device (5SGXEA7N2F45C2). It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 13.0sp1.
This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGXEA7
Documentation
DocumentDescription
40Gbps Ethernet MACPHY IP Pause Control Demo DesignInterfaces
Development KitStratix V GX 100G Development Kit
Quartus Prime VersionDownload Quartus Prime v13.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 19, 2020, 4:22 p.m.