|Design Example \ Outside Design Store|
|40Gbps Ethernet MACPHY IP Pause Control Demo Design|
|This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GT device (5SGXEA7N2F45C2). It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 13.0sp1. |
This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels.
|Stratix V GX 100G Development Kit|
|Download Quartus Prime v13.0|