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100Gbps Ethernet CAUI-4 CFP2 Hardware Demo Design  


CategoryDesign Example \ Outside Design Store
Name100Gbps Ethernet CAUI-4 CFP2 Hardware Demo Design
DescriptionThis reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and CAUI-4 (4 x 25.7Gbps) PHY IP solution on a Stratix V GT device (5SGTMC7K3F40C2N). It is configured to demonstrate on a Stratix V GT 100G CFP2 Evaluation Board using Altera development tool Quartus II release 13.0.This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP2 module with 4 x 25.7Gbps full-duplex channels.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGXEA7
Documentation
DocumentDescription
100Gbps Ethernet CAUI-4 CFP2 Hardware Demo DesignInterfaces
Development KitStratix V GX 100G Development Kit
Quartus Prime VersionDownload Quartus Prime v13.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 19, 2020, 4:13 p.m.