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HiSPi Imager Connectivity Design Example   


CategoryDesign Example \ Outside Design Store
NameHiSPi Imager Connectivity Design Example
DescriptionThe High-Speed Pixel Interface (HiSPi) design example demonstrates the use of an Altera® Cyclone® V FPGA to capture streaming video from an Aptina HiSPi serial interface. The FPGA receives the pixel data from the imager.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CGTFD9
Documentation
DocumentDescription
HiSPi-
Development KitCyclone V GT FPGA Development Kit
Quartus Prime VersionDownload Quartus Prime v12.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Feb. 16, 2016, 10:32 p.m.