Design Store


AN 307: Altera Design Flow for Xilinx Users  


CategoryDesign Example \ Outside Design Store
NameAN 307: Altera Design Flow for Xilinx Users
DescriptionDesigning for Altera® Field Programmable Gate Array devices (FPGAs) is very similar, in concept and practice, to designing for Xilinx FPGAs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software and begin compiling your design to the target device. This document is intended for Xilinx designers who are familiar with the Xilinx ISE software and would like to convert their existing ISE designs to the Altera Quartus II software environment.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGSED6
Documentation
DocumentDescription
Document-
Development KitNon kit specific Stratix V Design Examples
Quartus Prime VersionDownload Quartus Prime v12.1
Quartus Prime EditionStandard
VendorIntel


Last updated on June 13, 2016, 7:58 p.m.