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AN 307: Altera Design Flow for Xilinx Users - Stratix IV  


CategoryDesign Example \ Outside Design Store
NameAN 307: Altera Design Flow for Xilinx Users - Stratix IV
DescriptionDesigning for Altera® Field Programmable Gate Array devices (FPGAs) is very similar, in concept and practice, to designing for Xilinx FPGAs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software and begin compiling your design to the target device. This document is intended for Xilinx designers who are familiar with the Xilinx ISE software and would like to convert their existing ISE designs to the Altera Quartus II software environment.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix IV
DeviceEP4S100G2ES
Documentation
DocumentDescription
Document-
Development KitNon Kit Specific Stratix IV Design Examples
Quartus Prime VersionDownload Quartus Prime v12.1
Quartus Prime EditionStandard
VendorIntel


Last updated on July 1, 2016, 2:06 p.m.