AN 307: Altera Design Flow for Xilinx Users - Stratix IV
|Design Example \ Outside Design Store|
|AN 307: Altera Design Flow for Xilinx Users - Stratix IV|
|Designing for Altera® Field Programmable Gate Array devices (FPGAs) is very similar, in concept and practice, to designing for Xilinx FPGAs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software and begin compiling your design to the target device. This document is intended for Xilinx designers who are familiar with the Xilinx ISE software and would like to convert their existing ISE designs to the Altera Quartus II software environment.|
|Non Kit Specific Stratix IV Design Examples|
|Download Quartus Prime v12.1|
Last updated on July 1, 2016, 2:06 p.m.