Design Store


40Gbps Ethernet MACPHY IP Reference Design  


CategoryDesign Example \ Outside Design Store
Name40Gbps Ethernet MACPHY IP Reference Design
DescriptionThis reference design demonstrates the operation of Altera® 40-Gbps Ethernet MAC and PHY IP solution on a Stratix V device (5SGXEA7N2F45C2ES). It is configured to demonstrate on a 100G Development Kit, Stratix V GX Edition Board using Altera development tool Quartus II release 12.1. This design provides a flexible test and demonstration platform which effectively control, test, and monitor 40Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGXEA7
Documentation
DocumentDescription
40Gbps Ethernet MACPHY IP Reference DesignInterfaces
Development KitStratix V GX 100G Development Kit
Quartus Prime VersionDownload Quartus Prime v12.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 19, 2020, 4:22 p.m.