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HiSPi (High-Speed Pixel Interface) Imager Connectivity Design Example  


CategoryDesign Example \ Outside Design Store
NameHiSPi (High-Speed Pixel Interface) Imager Connectivity Design Example
DescriptionThe High-Speed Pixel Interface (HiSPi) design example demonstrates the use of an Altera® Cyclone® V FPGA to capture streaming video from an Aptina HiSPi serial interface. The FPGA receives the pixel data from the imager.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone V
Device5CEFA7
Documentation
DocumentDescription
Documentation-
Development KitCyclone V E FPGA Development Kit
Quartus Prime VersionDownload Quartus Prime v12.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Feb. 26, 2016, 3:38 p.m.