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Reference Design - Arria V Hard Memory Controller Bonding Interface  


CategoryDesign Example \ Outside Design Store
NameReference Design - Arria V Hard Memory Controller Bonding Interface
DescriptionThis design demonstrates how to bond two 450MHz DDR3 SDRAM 32-bit UniPHY hard memory controllers to form a 450MHz 64-bit DDR3 SDRAM interface with a single master on Arria V FPGA. Same bonding guidelines is applicable to Cyclone V hard memory controller. This design is generated in Qsys flow. Simulation model and test bench generated by Qsys will be used to validate the functionality of the bonded hard memory controllers through simulation.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria V
Device5AGTFC7
Documentation
DocumentDescription
Reference Design - Arria V Hard Memory Controller Bonding InterfaceMemory and Memory Controllers
Development KitNon kit specific Arria V Design Examples
Quartus Prime VersionDownload Quartus Prime v12.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 20, 2020, 5:21 p.m.