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Altera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)  


CategoryDesign Example \ Outside Design Store
NameAltera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)
DescriptionAltera Timing Contraints Design Example for multiple Triple-Speed Ethernet (TSE) IP cores. The following two design examples demonstrate how to use the Altera MegaWizard generated SDC file to constrain timing when you have multiple Triple-Speed Ethernet (TSE) IP cores in your design.
-Design example 1: Multiple TSE IP cores (identical core configuration) with different IP output file names.
-Design example 2: Multiple TSE IP cores (identical core configuration) with the same IP output file name.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGSED6
Documentation
DocumentDescription
Altera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)Interfaces
Development KitNon kit specific Stratix V Design Examples
Quartus Prime VersionDownload Quartus Prime v12.0
Quartus Prime EditionStandard
VendorIntel


Last updated on April 9, 2017, 11:07 p.m.