Design Store


Altera Interlaken IP Throughput Measurement  


CategoryDesign Example \ Outside Design Store
NameAltera Interlaken IP Throughput Measurement
DescriptionThis application note describes a reference design that demonstrates Altera Interlaken IP throughput measurement for various size packets. It also provides a design example to demonstrate integrating the Interlaken IP core in user applications. The Interlaken IP variant in this reference design is configured with 20 lanes at 6.375 Gbps, providing a real time hardware environment to measure throughput for a 100G Ethernet packet application. A companion Microsoft Excel worksheet that is provided with the reference design calculates throughput for applications that use other Interlaken IP configurations. The worksheet provides throughput and user side clock frequencies for various transceiver configurations using different numbers of lanes and different line rates.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix V
Device5SGXEA7
Documentation
DocumentDescription
Altera Interlaken IP Throughput MeasurementTransceivers
Development KitStratix V GX FPGA Development Kit
Quartus Prime VersionDownload Quartus Prime v11.1
Quartus Prime EditionStandard
VendorIntel


Last updated on June 3, 2020, 11:28 a.m.