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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendorDownloads
  Variable Decimator - CYCLONE V SOC  Design Example \ DSPNon kit specific Cyclone V SoC Design ExamplesCyclone V15.1.0 Intel0
  Variable Decimator - MAX 10  Design Example \ DSPNon Kit Specific MAX 10 Design ExamplesMAX 1015.1.0 Intel0
  Variable Decimator - MAX 10  Design Example \ DSPNon Kit Specific MAX 10 Design ExamplesMAX 1016.0.0 Intel0
  Variable Decimator - MAX 10  Design Example \ DSPNon Kit Specific MAX 10 Design ExamplesMAX 1016.1.0 Intel0
  Variable Decimator - STRATIX III  Design Example \ DSPNon Kit Specific Stratix III Design ExamplesStratix III16.1.0 Intel0
  Variable Decimator - STRATIX III  Design Example \ DSPNon Kit Specific Stratix III Design ExamplesStratix III15.1.0 Intel0
  Variable Decimator - STRATIX III  Design Example \ DSPNon Kit Specific Stratix III Design ExamplesStratix III16.0.0 Intel0
  Variable Decimator - STRATIX IV  Design Example \ DSPNon Kit Specific Stratix IV Design ExamplesStratix IV15.1.0 Intel0
  Variable Decimator - STRATIX IV  Design Example \ DSPNon Kit Specific Stratix IV Design ExamplesStratix IV16.0.0 Intel0
  Variable Decimator - STRATIX IV  Design Example \ DSPNon Kit Specific Stratix IV Design ExamplesStratix IV16.1.0 Intel0
  Variable Decimator - STRATIX V  Design Example \ DSPNon kit specific Stratix V Design ExamplesStratix V16.1.0 Intel0
  Variable Decimator - STRATIX V  Design Example \ DSPNon kit specific Stratix V Design ExamplesStratix V16.0.0 Intel0
  Variable Decimator - STRATIX V  Design Example \ DSPNon kit specific Stratix V Design ExamplesStratix V15.1.0 Intel0
  Variable Integer Rate Decimation Filter Design Example  Design Example \ DSPNon Kit Specific Stratix III Design ExamplesStratix III10.0 Intel0
  Vector Interrupt Controller for CVSX  Design ExampleCyclone V SoC Development KitCyclone V16.0.0 Intel23
  Vegetable Sorting Machine Vision Reference Design  Design Example \ Outside Design StoreiW-RainboW-G17DCyclone V15.0.0 iWave Systems Technologies Pvt. Ltd.NA
Verilog HDL: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA  Design Example \ Outside Design StoreStratix IV GX FPGA Development KitStratix IV11.0 Intel3
Verilog HDL: Microcontroller I/O Expander  Design Example \ Outside Design StoreNon Kit Specific MAX 10 Design ExamplesMAX 1015.0.0 Intel2
Verilog: Coefficients Reload Design Example for FIR Compiler  Design Example \ Outside Design StoreNon Kit Specific Stratix III Design ExamplesStratix III10.0 Intel2
  Verilog: FFT With 32K-Point Transform Length  Design Example \ DSPNon Kit Specific Stratix III Design ExamplesStratix III10.0 Intel0